geometrical optimizing design of interconnection for deep sub-micrometer vlsi circuits 電路中互連線的幾何優(yōu)化設(shè)計(jì)
most of vlsi circuits are sequential circuits . sequential circuits can be simulated by symbolic finite state machine ( fsm ) vlsi系統(tǒng)中大部分是時(shí)序電路,時(shí)序電路可以用符號化的有限狀態(tài)機(jī)(finite-state-machine,簡稱fsm)來模擬。
the design method of the circuits has the characteristics of systematization and modularization, so it suits the implementation of the vlsi circuit of the continuous wavelet transform system 這類電路的設(shè)計(jì)方法具有系統(tǒng)化、模塊化的特點(diǎn),適合連續(xù)小波變換系統(tǒng)這樣的大規(guī)模電路的實(shí)現(xiàn)。
it details the ic design process and vlsi circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays 它詳細(xì)規(guī)定了集成電路設(shè)計(jì)過程和超大規(guī)模集成電路電路,包括門陣列,可編程邏輯器件和陣列,寄生電容,及輸電線路的延誤。
test is an indispensable task of vlsi circuits design . with the increased complexity of vlsi circuits, time overhead of atpg has become a bottleneck of design 隨著vlsi電路復(fù)雜性的增長,自動測試生成(atpg,automatictestpatterngeneration)的時(shí)間開銷已經(jīng)成為vlsi電路設(shè)計(jì)的瓶頸之一。